The invention relates to a method of testing an integrated circuit comprising a core and a plurality of memory cells having outputs and inputs which are alternately connected to inputs and outputs of the core, said core being provided with a clock input intended to receive a first clock signal in a standard mode of operation, each memory cell being identified by an address and provided with a clock input intended to receive a second clock signal in a test mode, said clock input of the core being subjected to a conditional inhibition in the test mode.
Such a method is described in U.S. Pat. No. 5,812,562. In accordance with the known method, the memory cells whose outputs are connected to the inputs of the core form a first test register, called control register, while the memory cells whose inputs are connected to the outputs of the core form a second test register, called observation register. Write access or read access from outside the integrated circuit to an i-order bit of one of the two registers is obtained, for example, by means of (i+1) shifts to the right of the content of the register. The address of the ith memory cell included in the register will thus be selected, which address serves to determine the number of shifts to which the register will be subjected.
When the integrated circuit is in the test mode, the clock input of the core is a priori inhibited and the core is in an idle state.
Testing a given operating sequence generally takes place in three stages:
In a first phase, called charging phase, the control register receives information from an external source, representing stimuli to be applied to the core so as to emulate a certain operating sequence. These stimuli simulate the environment to which the core will be subjected in case it would be ordered to execute said sequence in the standard operating mode. Such charging of the control register is clocked by means of the second clock signal. In a second stage, called emulation stage, the core must be restarted by means of a clock signal so as to enable to observe its responses to the stimuli present in the control register. In accordance with the known method, such a clock signal consists of a succession of pulses, the number of pulses being predetermined and stored in a clock register added to the control register, said two registers being simultaneously programmed during the charging phase associated with the test of each operating sequence, the number of pulses necessary for the core to complete each sequence being specific to said sequence.
The inhibition of the clock input of the core is then canceled and the core receives the number of clock pulses necessary to carry through the chosen operating sequence.
After said emulation phase, the observation register stores the signals present at the outputs of the core.
In a third phase, called validation phase, the value of the content of the observation register is compared with a digital reference value, which is representative of the response the core should supply in reaction to the stimuli received. In the case of identity between these values, it will be concluded that the core has correctly executed the chosen operating sequence.
The number of clock pulses necessary to emulate an operating sequence varies from sequence to sequence. Thus, the clock register should be of considerable size so as to be suitable for long operating sequences requiring a large number of clock pulses.
In the known method, the size of the clock register is of the order of 50% of the size of the control register. As these registers are charged bit by bit in accordance with a serial mode, the utilization of a clock register to generate clock pulses in the test mode causes an increase of the duration of the charging phase by 50%, and of the duration of the whole test of an operating sequence by 30 to 50%, depending on the duration of the emulation phase and the size of the observation register. Such an increase of the duration of the test according to the known method causes the production output to be reduced and the overall production cost of the integrated circuit to be increased considerably.
In addition, as the dimensions of the clock register are definitively fixed in the design stage of the integrated circuit, a large silicon surface must be used in order to be able to store the number of clock pulses in the test mode.
Moreover, an up-down counter must be used to check the number of clock pulses sent to the core, leading to a further increase in size of the surface of the integrated circuit wherein the known method is implemented.
It is an object of the invention to overcome these drawbacks by providing a method of testing an integrated circuit wherein the process of transferring clock pulses to the core in the test mode is carried out in a simple and flexible manner, without programming, inside a specific register, of a number of pulses specific to each operating sequence being necessary.
In accordance with the invention, a method as described in the opening paragraph comprises the following stages:
configuration of the circuit in the test mode,
selection of a so-called virtual address, which does not correspond to any memory cell,
canceling the inhibition of the clock input of the core for a predetermined period of time following said selection.
In accordance with this method, mere selection of a virtual address causes the transmission of a clock pulse to the clock input of the core. N successive selections of a virtual address enable a series of N clock pulses to be transferred to the core. Thus, pre-programming this number N in a register is no longer necessary, rendering the method in accordance with the invention very flexible, and resulting in savings regarding the silicon surface and the cost of production of the integrated circuit.
In a special embodiment in accordance with the invention, the clock input of the core receives the second clock signal when the inhibition of said clock input is canceled in the test mode.
Such an embodiment enables the integrated circuit to be clocked by means of the same second clock signal throughout the duration of the test mode, thereby avoiding clock switching which always turns out to be difficult to control.
In a variant of the invention, canceling the inhibition of the clock input of the core is additionally subject to the execution of an operation relative to the virtual address.
In accordance with this variant of the invention, the selection of a virtual address announces the forthcoming cancellation of the inhibition of the clock input, the duration of said cancellation of the inhibition, and hence the number of clock pulses transmitted to the core, being determined by the number of operations carried out with respect to said virtual address.
In an advantageous embodiment of this variant, canceling the inhibition of the clock input of the core is additionally subject to the execution of a predetermined specific operation relative to the virtual address.
In accordance with this embodiment, rather than detect every operation relative to a virtual address, it is sufficient to detect one specific operation, which leads to a simplification of the physical implementation of this phase, and hence to a reduction of its cost.
In a preferred embodiment of this variant, this predetermined specific operation is a shifting operation.
The choice of a shifting operation as a necessary condition for canceling the inhibition enables to use a series of instructions in accordance with the JTAG standard to control the transfer of a clock pulse to the core in the test mode.
In one of its embodiments, the invention also relates to an integrated circuit comprising:
a core provided with a clock input intended to receive a first clock signal in a standard operating mode,
a plurality of memory cells having outputs and inputs which are alternately connected to inputs and outputs of the core, each memory cell being identified by an address and provided with a clock input intended to receive a second clock signal in a test mode,
a control module intended to carry out an inhibition of the clock input of the core in the test mode, said control module being designed such that said inhibition will be canceled for a predetermined period of time after a virtual address, which does not correspond to any memory cell, has been selected.
In a variant of this embodiment, the control module is configured so as to transfer the second clock signal towards the clock input of the core when the inhibition of said input is canceled during the test mode.
In another variant of this embodiment, canceling the inhibition of the clock input of the core during the test mode is additionally subject to the execution of an operation relative to the virtual address.